1. Field of the Invention
The present invention generally relates to data caches for processors, or, more specifically, to sharing the data caches between processors.
2. Description of Related Art
The size of the various cache levels in a cache hierarchy—i.e., Level 1 (L1) cache, Level 2 (L2) cache, etc—remains an important design feature of modern computing systems. As a cache size increases, the computer system can store more data in the cache, however, this also increases the time required—i.e., the latency—for the processor to locate the data within the cache. Thus, larger caches have better hit rates but greater latency. Moreover, because caches are typically located proximate to the processors that request the data—e.g., on the same semiconductor chip where space is limited—increasing the size of the cache to store more data may not be possible. These considerations must be balanced when deciding the size of the cache memories.